This invention relates to electrical noise reduction in electronic analyzers, and particularly to an apparatus and method of reducing low frequency noise in analyzers that employ integrators that integrate sensor signals in industrial process monitoring systems.
There exists a class of analyzer for industrial process sensors that samples the sensor signals and integrates the sensor signals over a sample period. Commercial line power often affects these analyzers by inducing a voltage into the sensor signals. Because the induced signal is positive for one-half line frequency cycle and negative for one-half line frequency cycle, the effects of the induced line frequency cancels over the full line power cycle. Consequently, it is common to extend the sample period to equal some multiple of the line power cycle period. For example, a sample period of 100 milliseconds is a common standard because it is a multiple of the line power cycle periods for both 50 Hertz and 60 Hertz power. However, if the power frequency varies, noise is induced at a low xe2x80x9cbeatxe2x80x9d frequency. For example, if the sample period is 100 milliseconds (equal to 6 cycles of line power at 60 Hertz) and the actual line power is at 60.1 Hertz, a low frequency noise is induced into the analyzer at 0.1 Hertz. It is not practical to filter out low frequencies such as 0.1 Hertz. Consequently, where the analyzer operates on the line power, it has been common to monitor the line power frequency and synchronize the sample period to a multiple of the line power period. However, it is not possible or feasible to monitor line power in some devices. For example, where the analyzer is battery operated or operated by some other power source, such as an industrial process control two-wire communication link that supplies power to the analyzer from a central station, there is no effective way to monitor line power. Consequently, it is not possible to minimize low frequency noise due to induction of signals into the analyzer at line power frequency.
The present invention is directed to a technique of minimizing generation of low frequency noise induced by line power, thereby minimizing the adverse effects of the noise without monitoring line power.
A circuit according to the present invention includes an integrator arranged to integrate input signals over a predetermined sample period. The sample period is based on the period of a cycle of a power source at a base frequency, such as 50 or 60 Hertz, or both. A delay is coupled to the integrator and is responsive to the end of a sample period to delay start of a successive sample period for a predetermined time delay.
Noise induced into the circuit due to line power at the base frequency (e.g., 60 Hertz) cancels due to the equal amount of positive and negative portions of the noise over the entire sample period. Noise induced into the circuit due to line power that is not canceled over the entire sample period is cancelled during subsequent sample periods by induced noise that is out-of-phase with the previously induced noise.
The invention is particularly useful in environments where the circuit is not directly coupled to the line power source, such as in battery operated analyzers in industrial process control systems, and therefor cannot monitor the line power to synchronize the sample periods.
One aspect of the invention is a process of operating a circuit to minimize noise induced into the output signal of the circuit.